1. Technical Field
The present invention relates in general to a synchronizer used for providing a source synchronized bus and in particular to a synchronizer used for providing a source synchronized clock bus with multiple agents wherein the synchronized bus reduces the effect of clock skew during the signal capturing process.
2. Description of the Related Art
It is well known that providing a source synchronized bus reduces the effect of clock skew on the signal capturing process. After a signal is captured, the signal has to be transferred from the capture clock domain to an internal clock domain. A synchronizer is a circuit that accomplishes such a signal transfer from the capture clock domain to the internal clock domain.
However, a high performance source synchronized bus with multiple agents comprises a number of challenges and problems. For example, a first problem involves the timing of the capture and transfer signals. A long path (i.e. slow path delay) associated with a first cycle may lag behind a short path (i.e. fast path delay) of a second cycle. This first abnormality may result in erroneous signal capturing. Furthermore, a second problem is a situation that results from the separation of two signals of two different cycles for two different agents. The separation is reduced by many factors such as noise of reference voltage, time compression effect of space time relativity, and delay element variation. This second problem poses significant design challenges both in terms of control signal generation and noise margin of the synchronous latch.
It is therefore advantageous and desirable to provide a synchronizer used for providing a source synchronized clock bus with multiple agents wherein the synchronized bus reduces the effect of clock skew during the signal capturing process. It is also advantageous and desirable to provide a synchronizer that overcomes or resolves the problem involving the timing of the capture and transfer signals wherein a long path (i.e. slow path delay) associated with a first cycle may lag behind a short path (i.e. fast path delay) of a second cycle. It is further advantageous and desirable to provide a synchronizer that eliminates or minimizes erroneous signal capturing that results from the signal capture and transfer timing problem. It is still also advantageous and desirable to provide a synchronizer that overcomes or helps resolve the problem of the reduction of separation of two signals of two different cycles for two different agents wherein the reduction is a result of many factors such as noise of reference voltage, time compression effect of space time relativity, and delay element variation. It is still further advantageous and desirable to provide a synchronizer that has a design with control signal generation and noise margin of the synchronous latch that overcomes the reduction problem of the separation of the two signals.
It is therefore one object of the present invention to provide a synchronizer used for providing a source synchronized clock bus with multiple agents wherein the synchronized bus reduces the effect of clock skew during the signal capturing process.
It is another object of the present invention to provide a synchronizer that overcomes or resolves the problem involving the timing of the capture and transfer signals wherein a long path (i.e. slow path delay) associated with a first cycle may lag behind a short path (i.e. fast path delay) of a second cycle.
It is a further object of the present invention to provide a synchronizer that eliminates or minimizes erroneous signal capturing that results from the signal capture and transfer timing problem.
It is still another object of the present invention to provide a synchronizer that overcomes or helps resolve the problem of the reduction of separation of two signals of two different cycles for two different agents wherein the reduction is a result of many factors such as noise of reference voltage, time compression effect of space time relativity, and delay element variation.
It is still a further object of the present invention to provide a synchronizer that has a design with control signal generation and noise margin of the synchronous latch that overcomes the reduction problem of the separation of the two signals.
The foregoing objects are achieved as is now described. A synchronizer used for providing a source synchronized clock bus with multiple agents wherein the synchronized bus reduces the effect of clock skew during the signal capturing process. Generally, a set of two latches coupled sequentially is used to latch and transfer data wherein the first latch is a capture latch and the second latch is a storage latch. The output of both of these two latches are fed selectively to the internal latch. Since strobe signals with a full differential are immune to reference voltage noise delay variation, the strobe signals from the sending chip are selected as the base of all controls. The present synchronizer comprises at least one capture latch in the capture clock domain for capturing the signal, at least one storage latch for storing the signal coupled to the at least one capture latch, a multiplexer coupled to the at least one storage latch wherein the multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch, and an internal latch in the internal clock domain coupled to the multiplexer. The signal is controlled and processed by strobe signals and clock signals from the sending chip. A first group of control signals is used for latching data of the signal from the at least one storage latch and the at least one capture latch to the internal latch, and a second group of control signals is used for deriving the first group of control signals.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.